The present invention relates generally to under-bond pad structures suitable for use in integrated circuit devices having active circuits located under the bond pads.
Integrated circuits typically have a number of I/O pads that facilitate electrical connection to external devices. When an integrated circuit die is packaged, the I/O pads may be electrically connected to other devices using a variety of conventional techniques. One popular electrical connection technique is wire bonding which contemplates thermosonically (or otherwise) bonding a very thin (typically gold) wire to the I/O pad (which is often referred to as a “bond pad”). Conventional wire bonding techniques impart a significant amount of stress to the bond pads and therefore cracks are often observed in dielectric layers that underlie the bond pads.
Because of the problems that may be caused by wire bonding, it is common to avoid placing active circuits in regions of the die that are positioned immediately below the bond pads. This helps reduce the risk of wire bonding causing significant degradation of active circuits within the die. However, since the bond pads occupy significant die “real estate” (i.e., a significant percentage of the total surface area of the die), prohibiting the placement of active circuits in regions below the bond pads has the undesirable side effect of increasing the required die size. Accordingly, a number of bond pad designs have been proposed and/or developed that permit active circuits to be placed below the bond pad structures. Although some of the existing structures work well for this purpose, there are continued efforts to develop improved bond pad structures for use in integrated circuits.